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preliminary 16-mbit (1m x 16) pseudo static ram cyu01m16zcc mobl3? cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05602 rev. *c revised april 13, 2005 features ? wide voltage range: 2.2v?3.6v ? access time: 55 ns, 70 ns ? ultra-low active power ? typical active current: tbd @ f = 1 mhz ? typical active current: tbd @ f = f max ? ultra low standby power ? 16-word page mode ? automatic power-down when deselected ? cmos for optimum speed/power ? deep sleep mode ? offered in a lead-free 48-ball bga package ? operating temperature: ?40c to +85c functional description [1] the cyu01m16zcc is a high-performance cmos pseudo static ram organized as 1m words by 16 bits that supports an asynchronous memory interfac e. this device features advanced circuit design to provide ultra-low active current. this is ideal for providing more battery life? (mobl ? ) in portable applications such as cellular telephones. the device can be put into standby mode when deselected (ce high or both bhe and ble are high). the input/output pins (i/o 0 through i/o 15 ) are placed in a high-impedance state when: deselected (ce high), outputs are disabled (oe high), both byte high enable and byte low enable are disabled (bhe , ble high), or during a write operation (ce low and we low). writing to the device is accomplished by taking chip enable (ce low) and write enable (we ) input low. if byte low enable (ble ) is low, then data from i/o pins (i/o 0 through i/o 7 ), is written into the locati on specified on the address pins (a 0 through a 19 ). if byte high enable (bhe ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 19 ). reading from the device is accomplished by taking chip enables (ce low) and output enable (oe ) low while forcing the write enable (we ) high. if byte low enable (ble ) is low, then data from the memory location specified by the address pins will appear on i/o 0 to i/o 7 . if byte high enable (bhe ) is low, then data from memory will appear on i/o 8 to i/o 15 . refer to the truth table for a complete description of read and write modes. deep sleep mode is enabled by driving zz low. see the truth table for a complete description of read, write, and deep sleep mode. note: 1. for best-practice recommendations, please refer to the cypress application note ?system design guidelines? on http://www.cypr ess.com. 1m 16 ram array i/o 0 ?i/o 7 sense amps data in drivers oe i/o 8 ?i/o 15 we ble bhe power-down circuit bhe ble ce ce logic block diagram refresh/power-down circuit zz row decoder a 8 a 11 a 12 a 13 a 14 a 15 a 16 a 9 a 10 a 17 a 19 a 18 a 7 a 6 a 5 a 2 column decoder a 4 a 3 a 0 a 1
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 2 of 14 low-power modes at power-up, all four sections of the die are activated and the psram enters into its default state of full memory size and refresh space. this device prov ides four different low-power modes. 1. reduced memory size operation 2. partial array refresh 3. deep sleep mode 4. temperature controlled refresh reduced memory size operation in this mode, the 16-mb psram can be operated as a 12-mbit, 8-mbit and 4-mbit memory bloc k. please refer to ?variable address space register (var)? on page 4 for the protocol to turn on/off sections of the memory. the device remains in rms mode until changes to the variable address space register are made to revert back to a complete 16-mbit psram. partial array refresh the partial array refresh mode allows customers to turn off sections of the memory block in the stand-by mode (with zz tied low) to reduce standby current. in this mode the psram will only refresh certain portions of the memory in the stand-by mode, as configured by the user through the settings in the variable address register. once zz returns high in this mode, the psram goes back to operating in full address refresh. please refer to ?variable address space register (var)? on page 4 for the protocol to turn off sections of the memory in stand-by mode. if the var register is not updated after the power up, the psram will be in its default state. in the defau lt state the whole memory array will be refreshed in the stand-by mode. the 16-mbit mobl3? is divided into four 4-mbit sections allowing certain sections to be active (i.e., refreshed). deep sleep mode in this mode, the data integrity in the psram is not guaranteed. this mode can be used to lower the power consumption of the psram in an application. this mode can be enabled and disabled through var similar to the rms and par mode. deep sleep mode is activated by driving zz low. the device stays in the deep sleep mode until zz is driven high. pin configuration [2, 3] 48-ball vfbga we a 11 a 10 a 6 a 0 a 3 ce i/o 10 i/o 8 i/o 9 a 4 a 5 i/o 11 i/o 13 i/o 12 i/o 14 i/o 15 v ss a 9 a 8 oe v ss a 7 i/o 0 bhe zz a 17 a 2 a 1 ble v cc i/o 2 i/o 1 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 a 15 a 14 a 13 a 12 3 2 6 5 4 1 d e b a c f g h top view a 16 nc v cc a 18 nc a 19 product portfolio [4] product v cc range (v) speed (ns) power dissipation operating i cc (ma) standby i sb2 ( a) f = 1mhz f = f max cyu01m16zcc min. typ. [4] max. typ. [4] max. typ. [4] max. typ. [4] max. 2.2 3.0 3.6 55 tbd 5 tbd 35 tbd 60 70 25 notes: 2. ball h6 and e3 can be used to upgrade to a 32m and a 64m density respectively. 3. nc ?no connect? - not connected internally to the die. 4. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ) and t a = 25c. tested initially and after any design changes that may affect the parameter.
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 3 of 14 variable address mode register (var) update [5, 6] deep sleep mode?entry/exit [7] var update and deep sleep mode timing [5, 6] parameter description min. max. unit t zzwe zz low to write start 1 s t cdr chip deselect to zz low 0 ns t r [7] operation recovery time (deep sleep mode only) 200 s t zzmin deep sleep mode time 8 s notes: 5. oe and the data pins are in a don?t care state wh ile the device is in variable address mode. 6. all other timing parameters are as shown in the data sheets. 7. t r applies only in the deep sleep mode. address t wc ce bhe / ble we zz t aw t pwe t bw t sa t zzwe t ha lower-order address (a0-a4) low power modes t zzmin deep sleep mode ce or ble / bhe t cdr t r zz t zzmin
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 4 of 14 page mode this device can be operated in a page read mode. this is accomplished by initiating a normal read of the device. in order to operate the device in page mode, the upper order address bits should be fixed for four-word page access operation, all address bits except for a1 and a0 should be fixed until the page access is completed. for an eight-word page access, all address bits, except for a2, a1, and a0, should be fixed. for a sixteen-word page mode all address bits, except for a3, a2, a1, and a0, should be fixed. the supported page lengths are four, eight, and sixteen words. random page read is supported for all three four, eight, and sixteen-word page read options. therefore, any address can be used as the starting address. please refer to the table below for an overview of the page read modes. variable address space register (var) variable address space?address patterns partial array refresh mode (a3=0, a4=1) a2 a1, a0 refresh section address size density 0 1 1 1/4 th of the array 00000h - 3ffffh (a19 = a18 = 0) 256k x 16 4m 0 1 0 1/2 th of the array 00000h - 7ffffh (a19 = 0) 512k x 16 8m 0 0 1 3/4 th of the array 00000h - bffffh (a19:a18 not equal to 11) 768k x 16 12m 1 1 1 1/4 th of the array c0000h - fffffh (a19 = a18 = 1) 256k x 16 4m 1 1 0 1/2 th of the array 80000h - fffffh (a19 = 1) 512k x16 8m 1 0 13/4 th of the array 40000h - fffffh (a19:a18 not equal to 00) 786k x16 12m reduced memory size mode (a3=1, a4=1) 0 1 1 1/4 th of the array 00000h - 3ffffh (a19 = a18= 0) 256k x 16 4m 0 1 0 1/2 th of the array 00000h - 7ffffh (a19 = 0) 512k x 16 8m 0 0 1 3/4 th of the array 00000h - bffffh (a19:a18 not equal to 1 1) 768k x 16 12m 0 0 0 full array 00000h - fffffh (default) 1m x 16 16m 1 1 1 1/4 th of the array c0000h - fffffh (a19 = a18 = 1) 256k x 16 4m 1 1 0 1/2 th of the array 80000h - fffffh (a19 = 1) 512k x 16 8m 1 0 1 3/4 th of the array 40000h - fffffh (a19:a18 not equal to 00) 768k x 16 12m 1 0 0 full array 00000h - fffffh (default) 1m x 16 16m a0 a1 a2 a3 a4 a19 ? a5 memory array selection 11 ? 4m 10 ? 8m 01 ? 12m 00 ? 16m(default) top/bottom half selection 0 ? bottom (default) 1 ? top array on/off on zz 0 ? par mode (default) 1 ? rms mode zz enable/disable 0 ? deep sleep enabled 1 ? deep sleep disabled (default) reserved (rfu) page mode feature 4-word mode 8-word mode 16-word mode page length 4 words 8 words 16 words page read corresponding addresses a1, a0 a2, a1, a0 a3, a2, a1, a0 page read start address don't care don't care don?t care page direction don't care don't care don?t care
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 5 of 14 power-up characteristics the initialization sequence is shown in the figure below. chip select (ce ) should be high for at least 200 s after v cc has reached a stable value. no access must be attempted during this period of 200 s. parameter description min. typ. max. unit tpu chip enable low after stable v cc 200 s tpu ce v cc first access stable power
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 6 of 14 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage to ground potential .?0.3v to v ccmax + 0.3v dc voltage applied to outputs in high z state [8, 9, 10] ......................?0.3v to v ccmax + 0.3v dc input voltage [8, 9, 10] .................. ?0.3v to v ccmax + 0.3v output current into outputs (low)............................. 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current .................................................... > 200 ma device range operating temperature (t a )v cc cyu01m16zcc industrial ?40c to +85c 2.2v to 3.6v dc electrical characteristics (over the operating range) [8, 9, 10] parameter description test conditions cyu01m16zcc-55 ns cyu01m16zcc-70 ns unit min. typ. [4] max. min. typ. [4] max. v cc supply voltage 2.2 3.0 3.6 2.2 3.0 3.6 v v oh output high voltage i oh = ?0.1 ma v cc = 2.2v to 3.6v v cc ? 0.2 v cc ? 0.2 v v ol output low voltage i ol = 0.1 ma v cc = 2.2v to 3.6v 0.2 0.2 v v ih input high voltage v cc = 2.2v to 3.6v 0.8 * v cc v cc + 0.3v 0.8 * v cc v cc + 0.3v v v il input low voltage v cc = 2.2v to 3.6v ?0.3 0.2 * v cc ?0.3 0.2 * v cc v i ix input leakage current gnd < v in < v cc ?1 +1 ?1 +1 a i oz output leakage current gnd < v out < v cc ?1 +1 ?1 +1 a i cc v cc operating supply current f = f max = 1/t rc v cc = v ccmax i out = 0 ma cmos levels tbd 35 tbd 25 ma f = 1mhz tbd 5 tbd 5 ma i sb2 automatic ce power-down current ? cmos inputs ce > v cc ? 0.2v v in > v cc ? 0.2v or v in < 0.2v, f = 0, v cc =v ccmax tbd 60 tbd 60 a i zz deep sleep current v cc = v ccmax , zz < 0.2v, ce =high or bhe and ble =high 10 10 a capacitance [11] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, v cc = v cc(typ) 8pf c out output capacitance 8 pf notes: 8. v il(min) = ?0.5v for pulse durations less than 20 ns. 9. v ih(max) = v cc + 0.5v for pulse durations less than 20 ns. 10. overshoot and undershoot specifications ar e characterized and are not 100% tested. 11. tested initially and after any design or process changes that may affect these parameters.
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 7 of 14 thermal resistance [11] parameter description test conditions bga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia / jesd51. 56 c/w jc thermal resistance (junction to case) 11 c/w ac test loads and waveforms parameters 3.0v (v cc )unit r1 26000 ? r2 26000 ? r th 13000 ? v th 1.50 v switching characteristics over the operating range [12, 13, 14, 15] parameter description 55 ns 70 ns unit min. max. min. max. read cycle t rc [17] read cycle time 55 40000 70 40000 ns t cd chip deselect time ce , ble /bhe high pulse time 55 ns t aa address to data valid 55 70 ns t oha data hold from address change 5 5 ns t ace ce low to data valid 55 70 ns t doe oe low to data valid 25 35 ns t lzoe oe low to low z [13, 14, 16] 55 ns t hzoe oe high to high z [13, 14, 16] 20 25 ns t lzce ce low to low z [13, 14, 16] 10 10 ns t hzce ce high to high z [13, 14, 16] 20 25 ns t dbe ble /bhe low to data valid 55 70 ns t lzbe ble /bhe low to low z [13, 14, 16] 55 ns t hzbe ble /bhe high to high z [13, 14, 16] 20 25 ns notes: 12. test conditions for all parameters other than tri-state parame ters assume signal transition time of 1 ns/v, timing reference levels of v cc /2, input pulse levels of 0v to v cc , and output loading of the specified i ol /i oh as shown in the ?ac test loads and waveforms? section. 13. at any given temperature and voltage conditions t hzce is less than t lzce , t hzbe is less than t lzbe , t hzoe is less than t lzoe , and t hzwe is less than t lzwe for any given device. all low-z parameters will be measured with a load capacitance of 30 pf (3v) 14. t hzoe , t hzce , t hzbe , and t hzwe transitions are measured when the out puts enter a high -impedence state. 15. the internal write time of the memory is defined by the overlap of we , ce = v il , bhe and/or ble = v il . all signals must be active to initiate a write and any of these signals can terminate a write by going inactive. the data input set-up and hold timing should be referenced to the edg e of the signal that terminates the write 16. high-z and low-z parameters are characterized and are not 100% tested. 17. if invalid address signals shorter than min.trc are continuousl y repeated for 40us, the device needs a normal read timing (t rc ) or needs to enter standby state at least once in every 40 s. v cc v cc output r2 30 pf including jig and scope gnd 90% 10% 90% 10% rise time = 1 v/ns fall time = 1 v/ns output v th equivalent to: thevenin equivalent all input pulses r th r1
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 8 of 14 page read cycle t pc page mode read cycle time 20 40000 20 40000 ns t pa page mode address access 20 20 ns write cycle [15] t wc write cycle time 55 40000 70 40000 ns t sce ce low to write end 50 60 ns t aw address set-up to write end 50 60 ns t cd chip deselect time ce , ble /bhe high pulse time 55 ns t ha address hold from write end 0 0 ns t sa address set-up to write start 0 0 ns t pwe we pulse width 45 50 ns t bw ble /bhe low to write end 50 60 ns t sd data set-up to write end 25 25 ns t hd data hold from write end 0 0 ns t hzwe we low to high-z [13, 14, 16] 20 25 ns t lzwe we high to low-z [13, 14, 16] 10 10 ns switching characteristics over the operating range [12, 13, 14, 15] (continued) parameter description 55 ns 70 ns unit min. max. min. max.
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 9 of 14 switching waveforms read cycle 1 (address transition controlled) [19, 20] read cycle 2 (oe controlled) [18, 20] notes: 18. whenever ce , bhe / ble are taken inactive, they must rema in inactive for a minimum of 5 ns 19. device is continuously selected. oe , ce = v il . 20. we is high for read cycle. address data out previous data valid data valid t rc t aa t oha 50% 50% data valid t rc t ace t doe t lzoe t lzce high impedance t hzoe high oe ce i cc i sb impedanc e address v cc supply current t hzbe bhe / ble t lzbe t hzce data out t dbe t cd
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 10 of 14 page read cycle (zz = we = v ih , 16 word access) [17, 20] write cycle 1 (we controlled) [15, 16, 18, 21, 22] notes: 21. data i/o is high-impedance if oe > v ih . 22. during the don?t care period in the data i/o waveform, the i/os are in output state and input signals should not be applied. switching waveforms (continued) data valid doe data out t hzbe t oha oe ce t hzce bhe /ble a0-a3 t dbe t pc a4-a19 t aa data valid data valid data valid data valid data valid ace t data valid data valid t paa t lzce high z t rc t t hd t sd t pwe t sa t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe bhe / ble t bw don?t care t cd
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 11 of 14 write cycle 2 (ce controlled) [15, 16, 18, 21, 22] write cycle 3 (we controlled, oe low) [18, 22] switching waveforms (continued) t hd t sd t pwe t ha t aw t sce t wc t hzoe valid data ce address we data i/o oe don?t care bhe /ble t bw t sa valid data t hd t sd t lzwe t pwe t sa t ha t aw t sce t wc t hzwe ce address we data i/o t bw bhe / ble don?t care
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 12 of 14 write cycle 4 (bhe /ble controlled, oe low) [15, 18, 21, 22] switching waveforms (continued) t hd t sd t sa t ha t aw t wc valid data t bw t sce t pwe don?t care address ce bhe /ble we data i/o truth table [23,24] zz ce we oe bhe ble inputs/outputs mode power h h x x x x high z deselect/power-down standby (i sb ) h x x x h h high z deselect/power-down standby (i sb ) h l x x h h high z deselect/power-down standby (i sb ) h l h l l l data out (i/o 0 ?i/o 15 ) read active (i cc ) hlhlhldata out (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z read active (i cc ) h l h l l h data out (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z read active (i cc ) h l h h l l high z output disabled active (i cc ) h l h h h l high z output disabled active (i cc ) h l h h l h high z output disabled active (i cc ) h l l x l l data in (i/o 0 ?i/o 15 ) write (upper byte and lower byte) active (i cc ) h l l x h l data in (i/o 0 ?i/o 7 ); i/o 8 ?i/o 15 in high z write (lower byte only) active (i cc ) h l l x l h data in (i/o 8 ?i/o 15 ); i/o 0 ?i/o 7 in high z write (upper byte only) active (i cc ) l h x x h h high z deep power-down / par deep sleep (i zz ) / standby notes: 23. h = logic high, l = logic low, x = don?t care. 24. during zz = l and ce = h, mode depends on how the var is set up either in par or deep sleep modes.
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 13 of 14 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. mobl is a registered trademark and mob l3 and more battery life are trademarks of cypress semiconductor corporation. all product and company names mention ed in this document may be the trademarks of their respective holders. ordering information speed (ns) ordering code package name package type operating range 55 CYU01M16ZCCU-55BVXI bv48a 48-ball fine pitch vbga (6 mm 8 mm 1 mm) pb-free industrial 70 cyu01m16zccu-70bvxi bv48a 48-ball fine pitch vbga (6 mm 8 mm 1 mm) pb-free industrial package diagram 48-lead vfbga (6 x 8 x 1 mm) bv48a 51-85150-*b
preliminary cyu01m16zcc mobl3? document #: 38-05602 rev. *c page 14 of 14 document history page document title: cyu01m16zcc mobl3? 16-mbit (1m x 16) pseudo static ram document number: 38-05602 rev. ecn no. issue date orig. of change description of change ** 278869 see ecn syt new data sheet *a 280850 see ecn ref updated the ordering information to show lead-free offering. *b 314034 see ecn pci corrected part number added operating range in features section moved address lines a8 - a10 from column decoder to row decoder in the logic block diagram changed pin configuration diagram name from fbga to vfbga modified description on deep sleep mode changed t zzwe description changed ja and jc from 55 and 17 c/w to 56 and 11 c/w respectively changed r1, r2 and rth from 22000, 22000 and 11000 ? to 26000, 26000 and 13000 ? respectively modified test condition for i ix and i oz removed note # 18 from *a rev changed v cc(typ) to v cc in note # 12 changed v ol max., to 0.2 from 0.2 * v cc changed t oha from 10 ns to 5 ns changed t sce , t aw and t bw from 45 to 50 ns changed t rc and t wc from 6000 ns to 40000 ns changed t pc and t pa from 15 ns to 20 ns added parameter t cd in ac table and its corresponding footnote in notes section parameter t cd added in read cycle 2 and write cycle 1 timing diagrams changed from advance information to preliminary *c 351766 see ecn pci modified logic block diagram modified description on deep sleep mode deleted page write in th e page mode feature table added ce , bhe and ble in test conditions for i zz in dc table modified condition in the third row of the truth table for zz pin from x to h

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